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An Energy-Efficient Network-on-Chip Design using Reinforcement Learning.
Hao Zheng, Ahmed Louri: An Energy-Efficient Network-on-Chip Design using Reinforcement Learning. DAC 2019: 47
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Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging...
Avinash Karanth, Savas Kaya, Md. Ashif I. Sikder, Daniel Carbaugh, Soumyasanta Laha, Dominic DiTomaso, Ahmed Louri, Hao Xin, JunQiang Wu: Sustainability in Network-on-Chips by Exploring Heterogeneity...
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Dynamic Voltage and Frequency Scaling in NoCs with Supervised and...
Quintin Fettes, Mark Clark, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri: Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques. IEEE Trans. Computers...
View ArticleEditorial from the Incoming Editor-in-Chief.
Ahmed Louri: Editorial from the Incoming Editor-in-Chief. IEEE Trans. Computers 68(1): 3 (2019)
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Utility-based resource management in an oversubscribed energy-constrained...
Dylan Machovec, Bhavesh Khemka, Nirmal Kumbhare, Sudeep Pasricha, Anthony A. Maciejewski, Howard Jay Siegel, Ali Akoglu, Gregory A. Koenig, Salim Hariri, Cihan Tunc, Michael Wright, Marcia Hilton,...
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Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs.
Ahmed Louri, Jacques Henri Collet, Avinash Karanth: Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs. ACM J. Emerg. Technol. Comput. Syst. 15(1): 4:1-4:16 (2019)
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Dynamic Voltage and Frequency Scaling in NoCs With Supervised and...
Quintin Fettes, Mark Clark, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri: Dynamic Voltage and Frequency Scaling in NoCs With Supervised and Reinforcement Learning Techniques. Computer 52(9): 4-5 (2019)
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DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage...
Mark Clark, Yingping Chen, Avinash Karanth, Dongsheng Brian Ma, Ahmed Louri: DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning. IPDPS 2020:...
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4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs.
Talha Furkan Canan, Savas Kaya, Avinash Karanth, Ahmed Louri: 4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs. ICECS 2020: 1-4
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PIXEL: Photonic Neural Network Accelerator.
Kyle Shiflett, Dylan Wright, Avinash Karanth, Ahmed Louri: PIXEL: Photonic Neural Network Accelerator. HPCA 2020: 474-487
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A Versatile and Flexible Chiplet-based System Design for Heterogeneous...
Hao Zheng, Ke Wang, Ahmed Louri: A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. DAC 2020: 1-6
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CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design...
Ke Wang, Ahmed Louri: CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning. IEEE Trans. Parallel Distributed Syst. 31(9): 2125-2138 (2020)
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An Approximate Communication Framework for Network-on-Chips.
Yuechen Chen, Ahmed Louri: An Approximate Communication Framework for Network-on-Chips. IEEE Trans. Parallel Distributed Syst. 31(6): 1434-1446 (2020)
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Learning-Based Quality Management for Approximate Communication in...
Yuechen Chen, Ahmed Louri: Learning-Based Quality Management for Approximate Communication in Network-on-Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3724-3735 (2020)
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Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via...
Quintin Fettes, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri, Kyle Shiflett: Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning. IEEE Trans. Comput. Aided...
View ArticleState of the Journal.
Ahmed Louri: State of the Journal. IEEE Trans. Computers 69(4): 466-467 (2020)
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TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure...
Ke Wang, Hao Zheng, Ahmed Louri: TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. IEEE Micro 40(5): 56-63 (2020)
View ArticleAlbireo: Energy-Efficient Acceleration of Convolutional Neural Networks via...
Kyle Shiflett, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri: Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics. ISCA 2021: 860-873
View ArticleGCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional...
Jiajun Li, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu: GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks. HPCA 2021: 775-788
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Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore...
Hao Zheng, Ke Wang, Ahmed Louri: Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. HPCA 2021: 723-735
View ArticleCSCNN: Algorithm-hardware Co-design for CNN Accelerators using...
Jiajun Li, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu: CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters. HPCA 2021: 612-625
View ArticleBitwise Neural Network Acceleration Using Silicon Photonics.
Kyle Shiflett, Avinash Karanth, Ahmed Louri, Razvan C. Bunescu: Bitwise Neural Network Acceleration Using Silicon Photonics. ACM Great Lakes Symposium on VLSI 2021: 9-14
View ArticleScaling Deep-Learning Inference with Chiplet-based Architecture and Photonic...
Yuan Li, Ahmed Louri, Avinash Karanth: Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects. DAC 2021: 931-936
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ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for...
Yuan Li, Ahmed Louri: ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures. IEEE Trans. Sustain. Comput. 6(2): 274-288 (2021)
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Reduced Precision Redundancy for Reliable Processing of Data.
Shanshan Liu, Ke Chen, Pedro Reviriego, Weiqiang Liu, Ahmed Louri, Fabrizio Lombardi: Reduced Precision Redundancy for Reliable Processing of Data. IEEE Trans. Emerg. Top. Comput. 9(4): 1960-1971 (2021)
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Stochastic Dividers for Low Latency Neural Networks.
Shanshan Liu, Xiaochen Tang, Farzad Niknia, Pedro Reviriego, Weiqiang Liu, Ahmed Louri, Fabrizio Lombardi: Stochastic Dividers for Low Latency Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap....
View ArticleApproximate Network-on-Chips with Application to Image Classification.
Yuechen Chen, Ahmed Louri, Shanshan Liu, Fabrizio Lombardi: Approximate Network-on-Chips with Application to Image Classification. NAS 2022: 1-8
View ArticleFSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator...
Yingnan Zhao, Ke Wang, Ahmed Louri: FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture. ICCD 2022: 545-552
View ArticleSPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference.
Yuan Li, Ahmed Louri, Avinash Karanth: SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference. HPCA 2022: 831-845
View ArticleAdapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous...
Jiaqi Yang, Hao Zheng, Ahmed Louri: Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation. ACM Great Lakes Symposium on VLSI 2022: 287-292
View ArticleAGAPE: Anomaly Detection with Generative Adversarial Network for Improved...
Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, Ahmed Louri: AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. DATE 2022: 849-854
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SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure...
Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri: SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. IEEE Trans. Sustain. Comput. 7(3):...
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AdaPrune: An Accelerator-Aware Pruning Technique for Sustainable CNN...
Jiajun Li, Ahmed Louri: AdaPrune: An Accelerator-Aware Pruning Technique for Sustainable CNN Accelerators. IEEE Trans. Sustain. Comput. 7(1): 47-60 (2022)
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SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With...
Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri: SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. IEEE Trans. Parallel Distributed Syst. 33(11): 2834-2845 (2022)
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SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based...
Yuan Li, Ahmed Louri, Avinash Karanth: SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference. IEEE Trans. Parallel...
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Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip...
Hao Zheng, Ahmed Louri: Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design. IEEE Trans. Emerg. Top. Comput. 10(1): 223-236 (2022)
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A Delta Sigma Modulator-Based Stochastic Divider.
Xiaochen Tang, Shanshan Liu, Farzad Niknia, Pedro Reviriego, Ziheng Wang, Wei Tang, Ahmed Louri, Fabrizio Lombardi: A Delta Sigma Modulator-Based Stochastic Divider. IEEE Trans. Circuits Syst. I Regul....
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Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With...
Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth: Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap....
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Flumen: Dynamic Processing in the Photonic Interconnect.
Kyle Shiflett, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri: Flumen: Dynamic Processing in the Photonic Interconnect. ISCA 2023: 75:1-75:13
View ArticlePolyform: A Versatile Architecture for Multi-DNN Execution via Spatial and...
Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, Hao Zheng: Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration. ICCD 2023: 166-169
View ArticleARIES: Accelerating Distributed Training in Chiplet-Based Systems via...
Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, Hao Zheng: ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects. ICCAD 2023: 1-9
View ArticleVenus: A Versatile Deep Neural Network Accelerator Architecture Design for...
Jiaqi Yang, Hao Zheng, Ahmed Louri: Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications. DAC 2023: 1-6
View ArticleA Silicon Photonic Multi-DNN Accelerator.
Yuan Li, Ahmed Louri, Avinash Karanth: A Silicon Photonic Multi-DNN Accelerator. PACT 2023: 238-249
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Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips.
Yuechen Chen, Ahmed Louri, Shanshan Liu, Fabrizio Lombardi: Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips. IEEE Trans. Sustain. Comput. 8(1): 120-132 (2023)
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A Technique for Approximate Communication in Network-on-Chips for Image...
Yuechen Chen, Shanshan Liu, Fabrizio Lombardi, Ahmed Louri: A Technique for Approximate Communication in Network-on-Chips for Image Classification. IEEE Trans. Emerg. Top. Comput. 11(1): 30-42 (2023)
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Error-Resilient Data Compression With Tunstall Codes.
Shanshan Liu, Pedro Reviriego, Anees Ullah, Ahmed Louri, Fabrizio Lombardi: Error-Resilient Data Compression With Tunstall Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1963-1975 (2023)
View ArticleGShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural...
Jia-Jun Li, Ke Wang, Hao Zheng, Ahmed Louri: GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators. J. Comput. Sci. Technol. 38(1): 115-127 (2023)
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Versa-DNN: A Versatile Architecture Enabling High-Performance and...
Jiaqi Yang, Hao Zheng, Ahmed Louri: Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration. IEEE Trans. Parallel Distributed Syst. 35(2): 349-361 (2024)
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A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN...
Yuan Li, Ahmed Louri, Avinash Karanth: A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration. IEEE Trans. Parallel Distributed Syst. 35(1): 46-58 (2024)
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Morph-GCNX: A Universal Architecture for High-Performance and...
Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri: Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. IEEE Trans. Sustain. Comput. 9(2):...
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